With the continuous increase of the integrate degree of semiconductor devices, the critical dimension of transistors has become smaller and smaller. Reducing the critical dimension of transistors allows more transistors on a chip; and enhances the properties of semiconductor devices. However, with the rapid reduction of the size of transistors, the thickness of the gate dielectric layer and the working voltage of the transistors may not be changed accordingly, which increases the difficulties in suppressing the short channel effect. Thus, the leakage current of the channel region of the transistor is increased.
The gate structures of fin field-effect transistors (FinFETs) are designed as fin-like three-dimensional (3D) architects. The channel regions of the FinFETs protrude from the surface of the semiconductor substrate to form the fins. The gate structures cover the top and side surfaces of the fins. Thus, the reverse-type layers are formed on the sides of the channel regions; and the “on/off” of the channel regions can be controlled from multiple sides of the channel regions. Such a design increases the control ability of the gate structures on the channel regions. Thus, the short channel effect can be effectively controlled. However, the existing FinFETs still have the short channel effect.
To further reduce the short channel effect of the semiconductor devices and reduce the leakage current of the channel regions, one approach is to perform an anti-punch through ion implantation process. Such an ion implantation process reduces the possibility of the source-drain punch through and the short channel effect.
However, the existing fabrication methods including the anti-punch through ion implanting process of semiconductor structures are easy to affect the properties of the semiconductor structures. The disclosed semiconductor structures and methods are directed to solve one or more problems set forth above and other problems in the art.